Consider a sequence of five independent instructions running on a pipelined processor.

Vendor: ARM
Product: EN0-001
Update on: Jul 25, 2025
Questions: 210

ARM EN0-001 Question Answer

Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

5 cycles

7 cycles

8 cycles

15 cycles