In a Cortex-A processor, after which TWO of these events is a cache maintenance operation...

Vendor: ARM
Product: EN0-001
Update on: Jul 25, 2025
Questions: 210

ARM EN0-001 Question Answer

In a Cortex-A processor, after which TWO of these events is a cache maintenance operation required to ensure reliable code execution? (Choose two)

Processor reset

Switching from ARM to Thumb state

Changing the access permissions of a page

Executing a Data Memory Barrier instruction

Loading data from an unaligned memory address

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